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Low-Current, SPI-Compatible
Real-Time Clock
16
Maxim Integrated
DS1347
GROUND PLANE
VIA CONNECTION
GROUND PLANE
VIA CONNECTION
GUARD RING
SM WATCH CRYSTAL
LAYER 1 TRACE
LAYER 2 LOCAL GROUND PLANE
CONNECT ONLY TO PIN 4
GROUND PLANE VIA
VCC PLANE
VIA CONNECTION
GROUND PLANE
VIA CONNECTION
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0.1
F
SM CAP
DS1347
Figure 4. Crystal PCB Layout
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
8 TDFN-EP
T833+2
21-0137
90-0059
Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
Chip Information
PROCESS: CMOS
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